1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a capacitor with increased capacity in a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices conventionally include a volatile memory, RAM (Random Access Memory), and a non-volatile memory, ROM (Read Only Memory). It is well known that the data storage capacity of a semiconductor memory device, such as a typical dynamic random access memory (DRAM) device having an access transistor and a capacitor, depends primarily upon a static capacitance of the capacitor used. Therefore, in the case that the capacitance is not full enough, a read error may be often caused during writing and reading data in the memory device. To prevent such a data error from occurring usually entails a refresh operation of re-storing data into the memory device after a lapse of a predetermined duration. As this refresh operation is significantly subject to the capacitance of a memory device, increase of such a capacitance is one of the most important ways for improving the refresh characteristic of the memory device. In the present state of the art, as integration of a semiconductor memory device becomes greater, an area of a unit memory cell per chip becomes smaller. Accordingly, an area capable of fabricating a capacitor in the memory cell is apt to decrease.
In general, capacitance is proportional to a cross-sectional area in contact with a storage electrode, serving as a lower electrode, and a plate electrode, serving as an upper electrode. It is in inversely proportional to a distance between these two electrodes. Accordingly, to form a lower electrode having more surface area available within a limited same substrate area of a semiconductor chip, the state of the art widely used a CUB (Capacitor Under Bit-line) structure forming a capacitor beneath the bit-line, and a COB (Capacitor Over Bit-line) process forming a capacitor over the bit-line. This combination results in the manufacture of a three-dimensional structure of stacked capacitors such as cylinder-type, box-type, fin-type, etc.
In addition to many attempts for improvement of the structure of a lower electrode as discussed above, various other solutions have been proposed in the art to achieve increase of the capacitance. These various other proposals utilize particular physical properties of conductive material used in the lower electrode. One of these proposed solutions is known as a crystal seeding. In a crystal seeding, a lower electrode surface of a capacitor is formed in curved polycrystalline silicon having a hemispherical grain or mushroom-like shape to increase its capacitance. Formation of a hemisphere-type silicon on the lower electrode surface, by using such a crystal seeding method, leads to an increase of the lower electrode surface area by about two to three times in comparison. Thus, the capacitor is able to provide improved capacitance over a usual one having no hemispherical silicon, up to about 1.8 times higher capacitance with a same chip area. Such a Hemi-Spherical Grain (HSG) silicon of lower electrode is disclosed in a publication entitled xe2x80x9cExtended Abstracts of the International Conference on Solid State Device and Materialsxe2x80x9d at pages 422 to 424, and also in U.S. Pat. No. 5,385,863 to Tatsumi Toru, et al. These references are hereby incorporated into the present application by reference.
Recently, active research has been performed to develop an MDL (Merged DRAM with Logic) device that incorporates a DRAM device and a logic circuit both manufactured to form a single component. Because this MDL component is formed within a single component, it is well known in the art that it provides significant advantage in terms of integration of semiconductor devices. In practice, it may have a wide range of applications in fabrication of very high scale semiconductor memory devices. Such an MDL device, however, is subject to a certain design rule or some limitation in design, which frequently causes an undesirable increase of evaporation depth in an insulation layer for forming a conductive layer for a capacitor lower electrode if more capacitance is to be pursued upon manufacturing of a stacked capacitor. As a result, a so-called step difference (coverage) from peripheral component regions becomes more critical, so it may often lead to a disadvantage that resolution deteriorates in a photo-lithographic etching process for patterning a thickened conductive layer.
Accordingly, the present state of the art recently departed from the conventional method of making a capacitor lower electrode by means of patterning it after overall evaporation of the conductive layer. Now, the current state of the art tends to prefer a sort of reverse patterning process of making the capacitor lower electrode by forming an opening for a capacitor lower electrode in an insulation layer and then filling up the opening with the conductive layer.
Referring now to FIGS. 1a to 1d, a prior art method for making a CUB type of capacitor will be explained. FIG. 1a illustrates an active region of a semiconductor substrate 10 having a component isolation layer 12. Additionally, a polycrystalline silicon layer 16 is formed through a gate oxide layer 14 to form a gate region. Subsequent to the formation of a spacer 18 with an insulation layer in a side wall of the polycrystalline silicon layer 16, an impurity diffusion region 20 serving as a source and a drain is then formed. The impurity diffusion region 20 is formed by utilizing the gate region of the spacer 18 as a self-aligned ion implantation mask, thereby finalizing an access transistor.
Consequently, after overall evaporation of a conductive layer onto the above resulting component, a photo-lithographic etching process is performed thereon to form a landing pad 22 contacting the impurity diffusion region 20 between the gate regions. Thereafter, by using Chemical Vapor Deposition (CVD), the evaporation of Phosphorus Silicon Glass (PSG), Boron Phosphorus Silicon Glass (BPSG), or Undoped Silicon Glass (USG) is applied to form an interlayer insulation layer 24. Next, a silicon nitride layer 26 is formed on this insulation layer 24. Further, an opening 28 is formed through the silicon nitride layer 26 and interlayer insulation layer 24 to expose the landing pad 22 by using a photosensitive pattern (not shown). More particularly, the landing pad is in contact with the source region of the impurity diffusion region 20.
Referring to FIG. 1b, it is shown that a conductive layer, having a depth of about 1,000 angstrom, and serving as a lower electrode of a capacitor, is formed entirely on a semiconductor substrate 10 having an opening 28 thereon, and the impurities are then to be implanted thereto. Thereafter, a known crystal seeding is introduced to make a growth of hemispherical silicon on the surface of the conductive layer for forming a lower electrode 30 of the capacitor. Then, an oxide layer 32 is further formed on this resultant layer of the lower electrode.
As shown in FIG. 1c, a planarization process such as etch-back or CMP is performed onto the resultant layer of oxide layer 32, preferably until a silicon nitride layer 26 is exposed. Next, the oxide layer 32 is completely removed through a wet etching process.
Referring finally to FIG. 1d, an oxide-nitride-oxide (ONO) layer 34 serving as a high dielectric substance layer on the aforementioned resultant layer is formed. The formation of this ONO layer may be made from a series of processes as follows: for example, first performing an oxidation process for 30 seconds at a temperature of 750xc2x0 C. to form an oxide layer having a depth of about 10 angstrom; then, forming a nitride layer having a depth of about 55 angstrom or less on the oxide layer; and performing a second oxidation process for about 30 seconds at the same temperature to form an oxide layer having a depth of about 10 angstrom; next, polycrystalline silicon is evaporated onto the ONO layer; and then, by patterning the polycrystalline silicon layer, a plate electrode 36 serving as an upper layer of a capacitor is formed.
According to the aforementioned prior art method for CUB capacitor, there may be some advantages in that it may prevent degrading of resolution by depth of the conductive layer for a lower electrode of a capacitor since it utilizes a reverse patterning. It still has a critical disadvantage, however, of a decrease of capacitance in the capacitor. Further, in case the interlayer insulation layer 24 and the silicon nitride layer 26 are removed to obtain more capacitance, an evaporation process for the interlayer insulation layer should be performed once again in order to make a contact to a gate in the logic region. Thus, this will lead to significant difficulties in manufacturing the capacitors of the current state of the art.
It is therefore a feature of an embodiment of the present invention to provide a method for making a capacitor having increased capacitance without degraded resolution of a semiconductor memory device.
It is another feature of an embodiment of the present invention to provide a method for making a capacitor of a semiconductor memory device having increased capacitance without removal of any interlayer insulation layers upon formation of a lower electrode by using a reverse patterning method.
According to one aspect of the present invention, the method for fabricating a capacitor of a semiconductor memory device having a dielectric layer between a lower electrode and an upper electrode, includes the steps of:
after formation of an access transistor on a semiconductor substrate, forming a first interlayer insulation layer for planarization of a surface of the semiconductor substrate and a second interlayer insulation layer for formation of the capacitor lower electrode;
after formation of an opening for exposing a part of an impurity diffusion region of the access transistor by etching a part of the first and second interlayer insulation layers, forming a spacer within the opening;
after deposition of a conductive layer for the capacitor lower electrode onto a surface of the substrate on which the spacer is formed, performing a planarization process until a part of an upper surface of the spacer is exposed; and
after removal of the exposed spacer, forming the dielectric layer and the conductive layer for the upper electrode of the capacitor, in sequence.
According to a further aspect to the present invention, the method for fabricating a capacitor of a semiconductor memory device having a dielectric layer between a lower electrode and an upper electrode, includes the steps of:
after formation of an access transistor on a semiconductor substrate having at least a top surface, forming a landing pad contacting an impurity diffusion region of the access transistor;
depositing a first interlayer insulation layer for planarization of a surface of the semiconductor substrate in which the landing pad is formed;
depositing a second interlayer insulation layer for formation of the capacitor lower electrode on the first interlayer insulation layer, and then forming an opening for exposing the landing pad in contact with a part of the impurity diffusion region of the access transistor;
after deposition of an insulation layer onto the top surface of the substrate, etching the insulation layer, and thereby forming a spacer in an inner wall of the opening;
after deposition of a conductive layer for the capacitor lower electrode onto the top surface of the substrate on which said spacer is formed, performing a planarization process until a part of an upper surface of the spacer is exposed; and
after removal of the exposed spacer, forming the dielectric layer and the conductive layer for the upper electrode of the capacitor, and then forming a bit line in the landing pad contacting a part of the impurity diffusion region of the access transistor.
According to still another aspect of the present invention, the method for fabricating a capacitor of a semiconductor memory device includes the steps of:
after formation of an access transistor on a semiconductor substrate, forming a landing pad contacting an impurity diffusion region of the access transistor;
depositing a first interlayer insulation layer for planarization of a surface of the semiconductor substrate in which the landing pad is formed;
after forming an opening in the first interlayer insulation layer, forming a bit line in a part of the impurity diffusion region of the access transistor by forming a conductive material;
depositing a second interlayer insulation layer on the semiconductor substrate in which the bit line is formed, and thereon a third interlayer insulation layer for formation of the capacitor lower electrode;
after forming an opening in a given region of the third interlayer insulation layer, forming a spacer inside the opening;
forming a contact plug in the landing pad contacting the part of the impurity diffusion region of the access transistor by etching the first and second interlayer insulation layers exposed through the opening;
after deposition of a conductive layer for the capacitor lower electrode onto the substrate in which the contact plug has been formed, performing a planarization process until a part of the upper surface of the spacer is exposed; and
after removal of the partially exposed spacer, forming a conductive layer for the capacitor upper electrode and the dielectric layer.